The present invention relates in general to programmable state counters and, more particularly, to a high speed programmable state counter.
Programmable state counters are frequently used in communication networks for synchronizing and controlling data transfer. For example, the counter may keep track of the number of data bits received in a serial shift register, say one or two bits per count, and provide a "data stream received" signal flag to further processing logic upon receiving a predetermined number of data bits. The data bits can be clocked off the rising and falling edge transitions of the state counter. The programmable feature of the counter allows the user to select the number of bits to be received in the serial shift register before actuating the signal flag. Once the predetermined number of data bits are loaded into the serial shift register and the signal flag is activated, the data may be transferred to parallel latches for synchronous processing through the communication network.
Most, if not all, prior art programmable state counters include a string of flipflops connected for generating a predetermined series of states which are compared against the programmed input data pattern. When the state of shift counter matches the input data pattern, as detected by a second string of flipflops, the output of the programmable state counter generates the signal flag indicating the desired number of data bits have been received in the data shift register. A reset signal restarts the predetermined count sequence in preparation for the next cycle.
The prior art programmable state counters include combinational logic exclusive-NOR gates to perform the comparison between the programmed input data pattern and the predetermined states of the shift counter. Also in the shift counter, an exclusive-NOR gate and an OR gate is required in the feedback path. The combinational logic introduces gate delays thereby slowing the operation of the programmable state counter. Typical operating frequencies of prior art programmable state counters range from 50 MHz to 100 MHz. As the data transfer rates required for present and future communication systems continue to increase, the operating frequency of the programmable state counters must increase accordingly.
Therefore, a need exists for an improved programmable state counter having fewer gate delays in the comparison logic allowing operation at higher frequencies.